The
Future of Verification is Open Source Tools
Tom West, Principal Engineer, Broadcom Corp, Tempe AZ
It’s time to take a hard look at hardware verification languages (HVLs). Once you do, you will come to one conclusion, it’s the wrong choice. In fact, even if proprietary HVL tools were free, it’s advisable to pass them up. Open source tools such as SystemC are the only way to go for modeling and verification. The recent breakthroughs in open Source verification such as the SystemC Verification library (SCV) have made an impact so significant, that there is no other choice.
Breakthroughs with the SCV Library make all the difference
in adoption for mainstream users by adding capabilities such as data
intraspection, constraints, and randomized test generation. The Verification
Working Group of the Open SystemC Initiative (OSCI) made SCV available last
December. It now provides powerful
capabilities equivalent with proprietary verification languages, but goes far
beyond hardware verification. Models can
be shared by architects and verifiers, and across business units. Reuse has been enabled across disciplines
because the open source SystemC library and simulator have been merged with the
testbench capabilities of Testbuilder.
As a result, SystemC no longer can be regarded as just an architectural
analysis tool.
What’s wrong with HVL tools? Plenty. In today’s development environments there is a lot more to verification than functionally correct silicon. Software verification, architecture verification, and system verification all have an increasingly significant role in todays Devlopment environments. Its a massive verification effort in trying to prevent the functional errors that are responsible for more than 70 percent of silicon respins. This effort typically consumes more than 70% of an engineering teams’ time and resources.
At first, point tool vendors rushed in with HVLs like Specman and Vera that look like the answer. But in the long term, HVLs are like quicksand, sucking teams into proprietary, inflexible environments, removing choice and, in the end, providing no solutions for reuse or scheduling. On the other hand, Open Source tools SystemC and more importantly, the methodologies they represent stand ready to throw a rope to those in need.
Take my Broadcom experience. For hardware development, we need solutions for sharing IP across business units, and between product design and verification environments. That is, we want to share modeling IP within product, software and architecture teams and within design and verification teams. We want to use the same product IP, modeling and verification environment throughout generations of product development and we want to share IP across different phases of the development cycle, such as unit-level and system-level verification. HVL capabilities can only provide some but not complete solutions to these requirements..
But time is an enemy of reuse. For example, verification environments we developed just 1-1/2 years ago in Specman are impossible to use unless we resurrect old, outdated Specman software. Business units must archive and remember the operational differences of old tools. On top of these issues, we also had to worry about discontinued products. Remember Superlog?
There are other negatives with HVL, namely, the learning curve associated with HVLs imposes a significant stumbling block when accepting IP from another group. Also, there is a need to purchase expensive HVL tools and there are restrictions imposed by HVL environments whenever we try to share IP. As we become entrenched with HVLs and we lose flexibility, what happens? The cost of HVL tools goes up and you can forget about standardization of HVLs as well. That is an unrealistic expectation given the nature of today's EDA climate.
Be
warned. HVL tools spread like a virus, and once designed in, are almost
impossible to remove. We know of one major microprocessor company
that made the choice to standardize on HVLs three years ago, when there were few limited alternatives. Unfortunately, this company is now stuck with their
choice and no longer has alternative options.
Admittedly, buying
an HVL tool can be the best decision a verification manager can make to get the
verification task done because HVLs
provide the quickest, most efficient methodology to do the job. But
there is a cost associated with this decision.
First, the
environment needs to be fully understood by the design-verification,
design-engineering, software and architecture teams, which is a difficult
accomplishment with HVL tools because they are not the optimum and natural solution for these
teams. Second, engineers are
motivated to learn a proprietary language only if it is in their job
description, meaning that only design verification (DV) engineers will do
it. The features that make HVL tools successful require this dedicated DV expertise. Even then, some DV engineers will refuse to use some of the
competitive features that make HVLs the “right” choice. So while good for design verification, HVL
tools are not the best solution to serve the overall needs of a business unit
or the “greater good” of the development team.
By contrast, recent developments in open-source tools offer benefits far
beyond design verification, with minimal DV adversity.
With an open-source environment such as SystemC, users can achieve complete vendor independence while making use of vendor features. Designs can be resurrected and proliferated freely and quickly--anytime, anywhere across business units, with minimal impact. Version issues will also be resolved by modifying the open source code and taking advantage of a common language such as C/C++, which is already known by virtually every DE, VE, SWE, and architectural engineer throughout Broadcom and its customer base. Goodbye learning curve.
Naturally, nothing is perfect. SystemC is unsupported and vendors are still seeking some way to bring profitability to open source. Some items are missing as well, such as SCV extensions and documentation, but the gaps will be filled in over time. To help alleviate these issues and better exchange information on this subject, Broadcom has formed its own users group internally to share ideas and IP across Business Units.
With open modeling tools, system-level verification can be done throughout the lifetime of the project and the same verification components can be reused for both block verification, architectural exploration and optimization, as well as for software development.For verification, SystemC provides baseline HVL features and many of the features inherent in other hardware verification languages, such as Vera and Verisity's ‘e.’ SystemC has become the framework for the big picture in design, engineering, verification, reuse and beyond.
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