Open Verification Foundation
Your Hardly ever updated one Stop resource for everything needed for open domain, reusable, new generation, ASIC and SOC verification.
(Click Picture for disturbed humor)
This is a NO "Viral Verification Vendor" Site!
Founded, March 2001 And not realistically unpdated in many years. You may or may not want to waste your time here.
Mission
OVF provides code and methodologies
to show how the best features and capabilities of HVL tools such
as Specman and Vera can be accomplished in an open-source environment
while showing from a business level perspective how the benefits
of open-source environments can possibly outweigh any implementation
adversity. OVF will
show how one can eliminate the Viral Vendor dependencies propagated
by HVL tool vendors while proving a methodology showing "Bolt-On" vendor
value. OVF will provide a level of
support via discussions not otherwise obtainable from vendors due to
the open-source nature of the tools. OVF's main
focus will be initially on transitioning to SystemC.
*****Update*****
I have to suggest here that Synopsys is clearly the choice when choosing EDA tools!
Disclaimer:
This site is strictly
a hobby to develop and promote completely vendor independent verification
solutions. It is against
my mission to promote any vendor on this site or with postings on other
site forums. This
site is strictly a representation of a fun passion to test, and share new
ideas that often are not available from verification tool vendors. I
fully welcome the close scrutiny that this site is now receiving Cadence
and I would appreciate instant feedback if you feel I have crossed
the line.
Verilator Rules!
If you are considering a tool to translate Verilog RTL to SystemC
for real performance you really should check out Verilator from my links page. This easy to debug, open source solution rocks over vendor solutions such as Carbon Systems or Tni-Valiosys or Others.
New Featured Tool!
Check
out the link on the tools page for Oroboro/APVM (A
Python VPI Module). This object level abstraction library offers a
tight integration into any Verilog simulator. This is an exciting new
and promising addition. Thanks goes to Tom Sheffler.
*****Tool Links*****
Here is the meat of the site. A comprehensive set of open source
links for everything from synthesis to simulation to analysis. I
encourage contributions to this site especially for this page.
For those who just my site for Doxygen SystemC documentation, here are
the quick links:
(SystemC_with_SCV_2.01) or (SystemC_with_SCV_2.1beta11)
Give us your feedback - All contributions are welcomed and will be credited accordingly.
Related articles and documentation - A collection of notes, articles, to help one justify the verification strategies suggested on these web pages.
Documentation and tool comparison tables - Removed, (a bit outdated)
Choose this link for some feature comparison between SystemC with Specman, and
Vera.
Links to examples - Not complete, this is an ultimate goal of this site to show a complete vendor independent environment as an example.