( VG 3.15, Item 5 ) -------------------------------------------- [02/11/29]

Subject: Highest Performance from your HVL Tools with Fewer Licenses.

From: Tom West, Broadcom [twest1@cox.net]

The Problem:

• High Level Verification Language tools throttle performance of simulations when linked with RTL simulators through PLI.
• The price of the HVL tools is prohibitively expensive to use in regression mode if a one for one ratio of HVL to RTL simulation licenses are required as in the case with PLI linked environments.

Some Assumptions:

• Lets assume we have an environment that is unbounded by hardware processing horsepower. This is easy to achieve especially in the case where environments utilize banks of Linux OS on Intel processors.
• Lets assume we are unbounded by the quantity of RTL simulation licenses. This is easy to achieve as RTL simulation is now a commodity item.
• Lets assume we can generate stimulus at a rate 5 times faster than the RTL simulation tools can consume it (True for my experiment). This is easy to test for and is easily achieved in many environments even with complex stimulus generation schemes. A corollary to this assumption is that in a PLI linked environment, one could consider that the HVL tool is idle 80% of the time. Is this an efficient use of the premium priced HVL tool?

A Solution:

• Lets de-link the simulation tool from the RTL environment. Does this sound like a step backwards in progress? Yes, There allot of issues and features to give up, but lets focus on the up side.
• What if we could now use fewer HVL licenses than RTL simulator licenses? What if we could not only save license usage by using fewer simulator licenses, but gain considerable performance at the same time?

My experiments utilized 5 HVL licenses (Specman), 25 RTL simulation licenses (NC-Verilog) and 30 processors. The 5 HVL licenses are working on 5 processors generating stimulus and expected results to ASCII files. Multiple stimulus and expected result files get created by each processor, i.e. The environment creates many smaller tests rather than fewer longer tests. This ASCII file I/O approach gives me the advantage of simulation logging while creating stimulus and results.

A script kicks off all 5 HVL "generators" and monitors the completion of the expected result and stimulus file creation. As the files are generated, the same script kicks off RTL simulations on the other 25 processors. Each RTL simulation job would read the files, cycle the data into the RTL and produce simulation results to an output file.

The script then proceeds to do a cycle for cycle comparison on the expected results with the RTL results. If the comparison was correct the files would be deleted, including the waveform files to save disk space.

The Major Drawbacks:

• The reactive nature of the test bench environment is lost. The environment will have to be carefully planned to avoid the use of feedback from HDL simulator.
• Using the HVL tool for RTL functional coverage is not possible as it requires constant links through PLI. However we can write our own Verilog Models to perform basic RTL coverage, and coverage of the stimulus from the generation engine is still available in the HVL tool.

Summary:

The results I produced were crude but effective. The Ratio of 5 HVL licenses and processors to 25 RTL simulators and processors achieved almost perfect harmony of file creation to file consumption. With this approach I used 25 fewer HVL licenses, while increasing my simulation performance slightly over the PLI linked approach.

Another way to look at it is if I only had the 5 HVL licenses, I boosted my overall performance by slightly over 5x the PLI linked approach.