00001 00002 /***************************************************************************** 00003 00004 The following code is derived, directly or indirectly, from the SystemC 00005 source code Copyright (c) 1996-2004 by all Contributors. 00006 All Rights reserved. 00007 00008 The contents of this file are subject to the restrictions and limitations 00009 set forth in the SystemC Open Source License Version 2.3 (the "License"); 00010 You may not use this file except in compliance with such restrictions and 00011 limitations. You may obtain instructions on how to receive a copy of the 00012 License at http://www.systemc.org/. Software distributed by Contributors 00013 under the License is distributed on an "AS IS" basis, WITHOUT WARRANTY OF 00014 ANY KIND, either express or implied. See the License for the specific 00015 language governing rights and limitations under the License. 00016 00017 *****************************************************************************/ 00018 00019 /***************************************************************************** 00020 00021 sc_export.cpp -- 00022 00023 Original Author: Bishnupriya Bhattachary, Cadence, Design Systems, 00024 25 August, 2003 00025 00026 *****************************************************************************/ 00027 00028 /***************************************************************************** 00029 00030 MODIFICATION LOG - modifiers, enter your name, affiliation, date and 00031 changes you are making here. 00032 00033 Name, Affiliation, Date: 00034 Description of Modification: 00035 00036 *****************************************************************************/ 00037 00038 #include "systemc/communication/sc_export.h" 00039 00040 // ---------------------------------------------------------------------------- 00041 // CLASS : sc_export_base 00042 // 00043 // ---------------------------------------------------------------------------- 00044 00045 sc_export_base::sc_export_base() : sc_object(sc_gen_unique_name("export")) 00046 { 00047 simcontext()->get_export_registry()->insert(this); 00048 } 00049 00050 sc_export_base::sc_export_base(const char* name_) : sc_object(name_) 00051 { 00052 simcontext()->get_export_registry()->insert(this); 00053 } 00054 00055 sc_export_base::~sc_export_base() 00056 { 00057 simcontext()->get_export_registry()->remove(this); 00058 } 00059 00060 // called when construction is done 00061 00062 void 00063 sc_export_base::before_end_of_elaboration() 00064 { 00065 end_of_construction(); 00066 } 00067 00068 // called by before_end_of_elaboration (does nothing by default) 00069 00070 void 00071 sc_export_base::end_of_construction() 00072 {} 00073 00074 // called when elaboration is done (does nothing) 00075 00076 void 00077 sc_export_base::end_of_elaboration() 00078 {} 00079 00080 // called before simulation starts (does nothing) 00081 00082 void 00083 sc_export_base::start_of_simulation() 00084 {} 00085 00086 // called after simulation ends (does nothing) 00087 00088 void 00089 sc_export_base::end_of_simulation() 00090 {} 00091 00092 00093 // ---------------------------------------------------------------------------- 00094 // CLASS : sc_export_registry 00095 // 00096 // Registry for all exports. 00097 // FOR INTERNAL USE ONLY! 00098 // ---------------------------------------------------------------------------- 00099 00100 void 00101 sc_export_registry::insert( sc_export_base* export_ ) 00102 { 00103 if( m_simc->is_running() ) { 00104 SC_REPORT_ERROR(SC_ID_SC_EXPORT_AFTER_START_, export_->name()); 00105 } 00106 00107 #ifdef DEBUG_SYSTEMC 00108 // check if port_ is already inserted 00109 for( int i = size() - 1; i >= 0; -- i ) { 00110 if( export_ == m_export_vec[i] ) { 00111 SC_REPORT_ERROR(SC_ID_SC_EXPORT_ALREADY_REGISTERED_, export_->name()); 00112 } 00113 } 00114 #endif 00115 00116 /* 00117 //TBD: maybe we want to do this stuf for later 00118 00119 // append the port to the current module's vector of ports 00120 sc_module* curr_module = m_simc->hierarchy_curr(); 00121 if( curr_module == 0 ) { 00122 port_->report_error( SC_ID_PORT_OUTSIDE_MODULE_ ); 00123 } 00124 curr_module->append_port( port_ ); 00125 */ 00126 00127 // insert 00128 m_export_vec.push_back( export_ ); 00129 } 00130 00131 void 00132 sc_export_registry::remove( sc_export_base* export_ ) 00133 { 00134 if (size()==0) return; 00135 int i; 00136 for( i = size() - 1; i >= 0; -- i ) { 00137 if( export_ == m_export_vec[i] ) { 00138 break; 00139 } 00140 } 00141 if( i == -1 ) { 00142 SC_REPORT_ERROR(SC_ID_SC_EXPORT_NOT_REGISTERED_, export_->name()); 00143 } 00144 00145 // remove 00146 m_export_vec[i] = m_export_vec[size() - 1]; 00147 m_export_vec.decr_count(); 00148 } 00149 00150 // constructor 00151 00152 sc_export_registry::sc_export_registry( sc_simcontext& simc_ ) 00153 : m_simc( &simc_ ) 00154 { 00155 } 00156 00157 00158 // destructor 00159 00160 sc_export_registry::~sc_export_registry() 00161 { 00162 } 00163 00164 // called when construction is done 00165 00166 void 00167 sc_export_registry::construction_done() 00168 { 00169 for( int i = size() - 1; i >= 0; -- i ) { 00170 sc_export_base* e = m_export_vec[i]; 00171 if (e->get_interface() == 0) { 00172 SC_REPORT_ERROR(SC_ID_SC_EXPORT_NOT_BOUND_AFTER_CONSTRUCTION_, 00173 e->name()); 00174 } 00175 e->before_end_of_elaboration(); 00176 } 00177 } 00178 00179 // called when elaboration is done 00180 00181 void 00182 sc_export_registry::elaboration_done() 00183 { 00184 for( int i = size() - 1; i >= 0; -- i ) { 00185 m_export_vec[i]->end_of_elaboration(); 00186 } 00187 } 00188 00189 // called before simulation begins 00190 00191 void 00192 sc_export_registry::start_simulation() 00193 { 00194 for( int i = size() - 1; i >= 0; -- i ) { 00195 m_export_vec[i]->start_of_simulation(); 00196 } 00197 } 00198 00199 void 00200 sc_export_registry::simulation_done() 00201 { 00202 for( int i = size() - 1; i >= 0; -- i ) { 00203 m_export_vec[i]->end_of_simulation(); 00204 } 00205 } 00206 00207 00208 // Taf!
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